1. Technical Field
The present invention relates generally to an improved data processing system and in particular to a method and apparatus for an improved bus architecture in a data processing system. Still more particularly, the present invention relates to an improved method and apparatus for transferring data between devices on different buses within a data processing system.
2. Description of the Related Art
The use of a microprocessor and its associated bus architecture in a computer system is well known. Also well known is the coupling of peripheral components onto a bus for providing various other functions related to the computer system. Some examples of such devices are disk drives, disk drive controllers, graphics accelerators, audio cards, modems and network connections. Generally, these peripheral components are coupled to a system component bus, also referred to as a "secondary bus", for effecting data transfer between various components. Typically, with simpler computer systems, the data transfer is between the peripheral device and either the processor (CPU) or main memory.
In high performance computer systems, peripheral component interconnect (PCI) buses are often employed. The PCI bus is a high performance expansion bus architecture that was designed to replace the traditional ISA bus (Industry Standard Architecture bus) and EISA bus (Extended Industry Standard Architecture bus) buses found in many 886 based personal computers. A group of companies (including Intel, IBM, Compaq, DEC, Dell, NEC, etc.) cooperated in preparing and publishing a standard specification for the PCI bus. The specifications for the PCI bus is available from the PCI Special Interest Group, 5200 Elam Young Parkway, Hillsboro, Oreg.
In expanding the capacity of standard PCI, a "bus bridge", also referred to as a "PCI-to-PCI bridge", is employed. The primary function of such a bus bridge is to allow transactions to occur between a master device on one PCI bus and a target device on the other PCI bus. In this manner, the bus bridge provides system and adapter card designers an ability to overcome an electrical loading limits inherent in a standard PCI bus. A bus bridge has two interfaces, a primary interface and a secondary interface. The primary interface is the PCI interface of the bus bridge that is connected to the PCI bus closest to the central processing unit (CPU). The secondary interface is the PCI interface of the bus bridge that is connected to the PCI bus that is farthest from the CPU. Under the PCI bridge specifications, each of the interfaces are capable of either a master or target operation. With respect to the bus which initiates an operation, the bus bridge functions as a target on behalf of the target device that actually resides on the target bus. Likewise, with respect to the target bus, the bus bridge functions as a master on behalf of the master device that actually resides on the initiating bus.
In FIG. 1, a block diagram of a known data processing system architecture is illustrated. Data processing system 100 is a data processing system following the Intelligent Input/Output (I.sub.2 O) Architecture Specification, version 1.5, March 1997 available from the I.sub.2 O Special Interest Group. The specification describes an open architecture for developing device drivers in network system environments. The architecture is independent of the operating system (OS), processor platform, and system I/O bus.
Data processing system 100 is an example of an intelligent input/output (I.sub.2 O) architecture which includes a host central processing unit (CPU) 102 which could be a Pentium processor that is available from Intel Corporation located in Santa Clara, Calif. In an I.sub.2 O architecture, the host CPU 102 is responsible for running the various operating system modules (OSMs). In this example, the primary bus 104 is a PCI bus and provides communication between the host CPU 102, an input/output processor (IOP)/PCI bridge 106 and IOP 108. The IOP/PCI bridge 106 is intended to be a I.sub.2 O core compliant device such as Intel's i960. The IOP/PCI bridge 106 also contains a PCI-to-PCI bridge which bridges the primary bus 104 to the secondary bus 110, which in this example is also a PCI bus. Adapter #1 112 and adapter #2 114 are also attached to the secondary bus 110. Adapters 112 and 114 are non-intelligent, meaning that they contain no processor, and are reliant on external processing power to run their device drivers, or hardware driver module (HDM) in I.sub.2 O terminology. In this example, both of these adapters' (112 and 114) HDMs are actually running on the IOP/PCI bridge 106. IOP 108 is an example of an I.sub.2 O shell compliant device and is an intelligent adapter such as Symbios' SYMFC920. IOP 108 is specifically designed as an integral part of adapter #3 and is responsible for running adapter #3's HDM.
In a data processing system, such as the example system described in FIG. 1, in which there resides an IOP/PCI bridge and one or more additional IOPs it would be prudent to architect the system in such a way as to utilize more than one IOP on a given I/O transaction. Although bus bridges solve electrical loading limits inherent in standard PCI buses and I.sub.2 O offloads many I/O related tasks from the host CPU down to the various IOPS, there are still architectural issues when dealing with multiple inter-operating IOPs. Therefore, it would be advantageous to develop a simple method for allowing IOPs to inter-operate, share resources and distribute roe workload in such systems.